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| White Electronic Designs 1G- 128Mx64 DDR SDRAM UNBUFFERED FEATURES Clock speeds of 100MHz and 133MHz Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: 2.5V 0.20V JEDEC standard 184 pin DIMM package W3EG64129S-D3 PRELIMINARY* DESCRIPTION The W3EG64129S is a 124Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 128Mx4 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. OPERATING FREQUENCIES DDR266 @CL=2 Clock Speed CL-tRCD-tRP 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 June 2004 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG64129S-D3 PRELIMINARY PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 NC NC VCC PIN 47 48 49 50 51 52 53 54 55 56 57 56 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL NC A0 NC VSS NC BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS WP SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DQS9 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DQS10 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 A12 VSS DQ21 A11 DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DQS12 A3 DQ30 VSS DQ31 NC NC VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS NC A10 NC VCCQ NC VSS DQ36 DQ37 VCC DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DQS14 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS16 CK0, CK1, CK2 CK0#. CK1#, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC PIN NAMES Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect June 2004 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM CS1# CS 0# DQS0 DQ0 DQ1 DQ2 DQ3 DQS0 CS0# I/O3 I/O2 D0 I/O1 I/O0 W3EG64129S-D3 PRELIMINARY DQS8 DQ4 DQ5 DQ6 DQ7 DQS8 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS9 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS10 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS11 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS12 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS13 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS14 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS15 CS1# I/O3 I/O2 D0 I/O1 I/O0 DQS1 DQ8 DQ9 DQ10 DQ11 DQS1 CS0# I/O3 I/O2 D1 I/O1 I/O0 DQS2 CS0# I/O3 I/O2 D2 I/O1 I/O0 DQS3 CS0# I/O3 I/O2 D3 I/O1 I/O0 DQS4 CS0# I/O3 I/O2 D4 I/O1 I/O0 DQS5 CS0# I/O3 I/O2 D5 I/O1 I/O0 DQS6 CS0# I/O3 I/O2 D6 I/O1 I/O0 DQS9 DQ12 DQ13 DQ14 DQ15 DQS2 DQ16 DQ17 DQ18 DQ19 DQS10 DQ20 DQ21 DQ22 DQ23 DQS3 DQ24 DQ25 DQ26 DQ27 DQS11 DQ28 DQ29 DQ30 DQ31 CLOCK INPUT CK0/CK0# CK1/CK1# CK2/CK2# 5 SDRAMS 4 SDRAMS 6 SDRAMS 6 SDRAMS DQS4 DQ32 DQ33 DQ34 DQ35 DQS12 DQ36 DQ37 DQ38 DQ39 DQS5 DQ40 DQ41 DQ42 DQ43 DQS13 DQ44 DQ45 DQ46 DQ47 DQS6 DQ48 DQ49 DQ50 DQ51 DQS14 DQ52 DQ53 DQ54 DQ55 Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA DQS7 DQ56 DQ57 DQ58 DQ59 BA0 - BA1 A0-A12 CKE0 CKE1 RAS# CAS# WE# DQS7 CS0# I/O3 I/O2 D7 I/O1 I/O0 DQ0-D15 D0-D15 D0-D7 DQ8-D15 D0-D15 D0-D15 D0-D15 DQS15 DQ60 DQ61 DQ62 DQ63 VCCSPD VCC /V CCQ VREF VSS SPD D0 - D17 D0 - D17 D0 - D17 D0 D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS resistors: 22 Ohms. June 2004 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: W3EG64129S-D3 PRELIMINARY Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 16 50 Units V V C W mA Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0C TA 70C, VCC = 2.5V 0.2V Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Min 2.3 2.3 1.15 1.15 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 1.35 1.35 VCCQ + 0.3 VREF -0.15 -- VTT-0.76 Unit V V V V V V V V CAPACITANCE TA = 25C. f = 1MHz, VCC = 2.5V, VREF = 1.4V 200mV Parameter Input Capacitance (A0-A11) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CK0-2,CK0-2#) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 53 53 29 18 29 8 53 8 Unit pF pF pF pF pF pF pF pF June 2004 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS W3EG64129S-D3 PRELIMINARY Recommended operating conditions, 0C TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V Includes DDR SDRAM component only Parameter Operating Current Symbol IDD0 Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; PowerDown mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2 Max 2840 DDR266@CL=2.5 Max 2840 DDR200@CL=2 Max 2840 Units mA Operating Current IDD1 3040 3040 3040 mA Precharge PowerDown Standby Current Idle Standby Current IDD2P 95 95 95 rnA IDD2F 800 800 800 mA Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 800 1520 800 1520 800 1520 mA mA Operating Current IDD4R 3520 3520 3520 mA Operating Current IDD4W 4000 4000 4000 rnA Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 4960 80 7680 4960 80 7680 4960 80 7680 mA mA mA June 2004 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst W3EG64129S-D3 PRELIMINARY IDD7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. * * * * Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 June 2004 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR D3 Part Number W3EG64129S262D3 W3EG64129S265D3 W3EG64129S202D3 Speed 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2 2.5 2 tRCD 2 3 2 W3EG64129S-D3 PRELIMINARY tRP 2 3 2 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") PACKAGE DIMENSIONS FOR D3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 3.81 (0.150 MAX) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) June 2004 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 1GB - 128Mx64, DDR SDRAM UNBUFFERED W3EG64129S-D3 PRELIMINARY Revision History Rev # Rev A Rev 0 History Created Datasheet 0.1 Updated CAP and IDD specs. 0.2 Removed "ED" from part marking 0.3 Moved from Advanced to Preliminary Release Date 9-23-02 6-04 Status Advanced Primary June 2004 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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